Quiz  /  Verilog Gate & PSU MCQ Questions With Answers

  • 1. 
    Which is illegal in writing comments in verilog?

  • Embedding one-line comments in multiple-line comments
  • Embedding multiple-line comments in multiple-line comments
  • Embedding one-line comments after ;
  • all of the given

  • 2. 
    Verilog is case sensitive.

  • False
  • True

  • 3. 
    A + AB + ABC + ABCD + ABCDE can be reduced to

  • 1
  • 0
  • A
  • ABCDE

  • 4. 
    Which level of abstraction level is available in Verilog but not in VHDL?

  • Behavioral level
  • Structural level
  • Dataflow level
  • Switch level

  • 5. 
    Which logic level is not supported by verilog?

  • U
  • X
  • Z
  • None of the above

  • 6. 
    The processing of knowledge in an expert system is done by a program called

  • manipulator
  • calculator
  • inference engine
  • neumann machine

  • 7. 
    Which of the following vector part selection is considered ILLEGAL for the given example:wire [7:0] bus;reg [0:31] virtual_add;

  • bus[5]
  • bus[1:0]
  • virtual_add[5:0]
  • virtual_add[0]

  • 8. 
    What is wrong with following piece of code int a, b; initial begin forever begin a=a+1; b=b+1; end end

  • Nothing wrong
  • incorrect a and b can overflow as it is incremented in an infinite loop
  • Simulation may not advance since forever doesn't have any timing control
  • A forever block cannot be used inside an initial block

  • 9. 
    Femto second means ------------

  • 10 power -12
  • 10 power -16
  • 10 power -15
  • 10 power -09

  • 10. 
    Numbers that are specified without a specification are __________ numbers by default.

  • binary
  • decimal
  • octal
  • hexadecimal

  • 11. 
    In most synthesis tools, what will happen when a signal that is needed in a sensitivity list is not included?

  • An error will be generated and the code cannot be synthesized
  • A warning message will be generated and the code will be synthesized but the resulting netlist will not provide the desired results
  • The synthesis tool will ignore the sensitivity list since all objects that are read as part of a procedural assignment statement are considered to be sensitive
  • There will be no effect on the design and pre-synthesis simulation will be consistent with post-synthesis simulation

  • 12. 
    KV chart is an abbreviation for

  • Karnaugh-Veitch chart
  • Karnaugh-Verilog chart
  • Kenalog-Verilog chart
  • Kenalog-Veitch chart

  • 13. 
    VHDL uses an ___________declaration to describe how a component or block should perform

  • Architectural
  • Behavioral
  • Module
  • None of the above

  • 14. 
    Which of the following loops are supported by verilog?

  • if-else loop
  • for loop
  • while loop
  • All the above

  • 15. 
    Default value of a net is ___.

  • 0
  • 1
  • x
  • z

  • 16. 
    Verilog may be written at the

  • Behavioral level
  • Structural level
  • dataflow level
  • All the above

  • 17. 
    How many number of 3 to 8 decoders are used to design 4 to 16 decoder?

  • 5
  • 8
  • 2
  • 4

  • 18. 
    Reduced form of (a + b).(b+1) = ?

  • ab+b
  • ab+a+b
  • a+b
  • 1

  • 19. 
    Odd parity code for data 1110 is -----------------

  • 0
  • x
  • z
  • 1

  • 20. 
    Individual letters in a Boolean algebra expression are called

  • letters
  • lables
  • syllables
  • literals

  • 21. 
    For a 32-bit Windows, the specified number: 255 has how many bits?

  • 32
  • 16
  • 8
  • 4

  • 22. 
    A rule that specifies the default action to be taken when all other rules fail in a decision table is called

  • action stub
  • default rule
  • condition stub
  • definite rule

  • 23. 
    (B+C).D = BD + BD is an example for?

  • Absorption law
  • Distributive law
  • Commutative law
  • Identity law

  • 24. 
    Verilog HDL is a case-sensitive language. All keywords are in _________.

  • lowercase
  • uppercase
  • either lower or uppercase
  • bold letters
Report Question
warning
access_time
  Time